============================================================== Guild: wafer.space Community Channel: 📐 - Designing / 📦-cob Topic: Channel for discussing chip-on-board packaging options for wafer.space bare die. After: 2025-11-30 11:59 p.m. Before: 2026-01-01 12:00 a.m. ============================================================== [2025-12-01 2:20 a.m.] mithro_ And expensive! {Reactions} 💯 [2025-12-01 2:23 a.m.] kris____ how much does it compare to the other packages? [2025-12-01 2:24 a.m.] mithro_ I've seen prices like O($100) USD per package [2025-12-01 2:25 a.m.] kris____ ooh ouch 🥲 [2025-12-01 2:26 a.m.] kris____ time to buy a kiln and make some casts lol [2025-12-01 4:56 a.m.] rzioma I wonder if that is a real thing {Attachments} 2025-12_media/image0-BA0FC.jpg [2025-12-01 11:57 a.m.] mithro_ Kinda looks like reclaimed device? [2025-12-01 3:59 p.m.] mattvenn leadframe looks intact to me {Reactions} 👍 (2) [2025-12-01 4:33 p.m.] rzioma imho should be new {Attachments} 2025-12_media/image-CC97F.png {Reactions} ❤️ [2025-12-01 4:49 p.m.] kris____ what is that part? [2025-12-01 5:08 p.m.] rzioma I dunno, but I saw them on the other photos with new ceramic packages. Perhaps something that is used to hold them while bonding. [2025-12-01 5:11 p.m.] rzioma {Attachments} 2025-12_media/image0-59146.jpg [2025-12-01 5:11 p.m.] rzioma Maybe just part of the manufacturing process [2025-12-01 5:38 p.m.] mattvenn Yes exactly, after bonding it gets snipped off {Reactions} 👍 [2025-12-01 5:56 p.m.] kris____ ohh that’s interesting, the holes in the first one make it look like it can be daisy chained with other ones [2025-12-05 12:50 p.m.] algofoogle I think it normally is… it comes as a continuous strip. The one pictured has already been snipped off the strip. [2025-12-05 12:50 p.m.] algofoogle (I think) [2025-12-06 7:42 a.m.] mithro_ I've seen them come in large metal panels. [2025-12-09 3:00 a.m.] anfroholic Hey all, Just got some PCBs back today for prototyping and verification. *edit: also note these are HASL, while real versions will be ENIG. It didn't seem worth $75 for just pictures* {Attachments} 2025-12_media/20251208_205627-581E0.jpg 2025-12_media/20251208_205703-3BE6A.jpg 2025-12_media/20251208_205731-938C6.jpg 2025-12_media/20251208_205753-20FEF.jpg [2025-12-09 3:00 a.m.] anfroholic I will try and assemble a few tomorrow *no die, just mezzanine connectors and headers* [2025-12-09 3:04 a.m.] anfroholic Mezzanine connectors also arrived today. {Attachments} 2025-12_media/20251208_210338-44587.jpg 2025-12_media/20251208_210347-F8EBB.jpg [2025-12-09 3:11 a.m.] anfroholic Last night I also played for a few minutes with another layout for the wirebonders. This would also fit into a dip package layout. {Reactions} ❤️ [2025-12-09 3:11 a.m.] anfroholic {Attachments} 2025-12_media/image-54C56.png [2025-12-09 4:48 a.m.] algofoogle Delightful 🙂 I’m getting excited! {Reactions} 💜 [2025-12-09 5:15 a.m.] urish Diplightful! {Reactions} 💜 (2) [2025-12-09 8:15 a.m.] rzioma Great news! [2025-12-09 8:23 a.m.] rzioma Is there a minimum distance requirement between the chip and the binding pad on a PCB? I am thinkng about 0.5x1 chip but rotate 90 degrees for placement. [2025-12-09 8:24 a.m.] 246tnt I think 1.5x~2x the die thickness IIRC. [2025-12-09 8:25 a.m.] anfroholic Yes @tnt you are correct https://drive.google.com/file/d/1touEQHWAOTon_98TdiVLKKqsQ8RJJ1tP/view {Attachments} 2025-12_media/image-9FE58.png {Embed} https://drive.google.com/file/d/1touEQHWAOTon_98TdiVLKKqsQ8RJJ1tP/view Design Rule SCMicro .pdf [2025-12-09 8:26 a.m.] rzioma What is the expected thickness of the die? [2025-12-09 8:26 a.m.] anfroholic The ones I have are about 0.7mm [2025-12-09 8:26 a.m.] 246tnt Although the numbers here are way off. IIRC the chips won't be back grinded so it'll be more like 800 um if it's anything like the sky130/ihp ones. [2025-12-09 8:27 a.m.] anfroholic I also believe they will not be back grinded [2025-12-09 8:28 a.m.] anfroholic What I drew above is pushing pretty close to the limits in spots [2025-12-09 8:31 a.m.] rzioma @Andrew Wingate btw, those light blue outgoing lines? They don't (always) connect to the red pads. Are these the ideal wire "diretions"? [2025-12-09 8:32 a.m.] anfroholic I spent maybe 10 minutes on this. Just sharing for the sake of sharing. The lines you see are just the old lines from the old version and don't really mean anything {Reactions} 👍 [2025-12-09 8:32 a.m.] anfroholic Also @ReJ aka Renaldas Zioma When you all are saying DIP, what width DIP are you referring to? [2025-12-09 8:34 a.m.] rzioma {Attachments} 2025-12_media/Package_DIP24-40-18358.jpg [2025-12-09 8:34 a.m.] rzioma This one [2025-12-09 8:34 a.m.] anfroholic The wide version that's .6" between centers {Attachments} 2025-12_media/RoU9Q-7BC69.png {Reactions} 👍 (2) [2025-12-09 8:34 a.m.] anfroholic haha ok yeah!! [2025-12-09 8:34 a.m.] anfroholic Thank you [2025-12-09 8:35 a.m.] rzioma inches are hard! 🙂 {Reactions} 💜 (2) [2025-12-16 12:18 a.m.] mithro_ [2025-12-16 12:19 a.m.] mithro_ {Reactions} 💜 (3) [2025-12-16 5:14 a.m.] anfroholic Forgive the fact this is LTT, but this one is a factory tour of a fab, touches on packaging and a bunch of other steps we're working on. I thought it was pretty cool https://www.youtube.com/watch?v=ivLvsTnp9fI {Embed} Linus Tech Tips https://www.youtube.com/watch?v=ivLvsTnp9fI A Petabyte in the Palm of My Hand - Kioxia Factory Tour A huge thanks to KIOXIA for sponsoring this video and for giving us this once in a life time opportunity. You can learn more about KIOXIA at: https://www.KIOXIA.com We flew to Japan to tour KIOXIA’s Yokkaichi Plant; a facility the size of approximately 98 soccer fields that uses state of the art automation to build the flash memory that may j... 2025-12_media/maxresdefault-983C7.jpg [2025-12-16 5:19 a.m.] the.tearex I really enjoyed that video. better than the recent hisense tour, and even better than the intel video. [2025-12-16 5:19 a.m.] the.tearex It probably won’t be a great performer for LMG, but that doesn’t matter—it’s still cool {Reactions} 👍 [2025-12-16 5:30 a.m.] anfroholic Just assembled the first test COB. I think I pretty much like the form factor. With 70pins they hold on there pretty good. Some conversations with other people, they had mentioned mezzanine connectors to the a weak point, but these seem pretty solid. I think I'm pretty happy with them overall. {Attachments} 2025-12_media/0004-52B4E.JPG 2025-12_media/0005-C5B46.JPG 2025-12_media/cob_mez-293F2.JPG 2025-12_media/mobo_mez-4DF82.JPG 2025-12_media/0007-A6A83.JPG 2025-12_media/0006-A89EE.JPG 2025-12_media/0011-85AC9.JPG {Reactions} waferspace (4) [2025-12-16 8:40 a.m.] rzioma I love the small metallic rocket in the corner! {Reactions} 💜 [2025-12-16 8:41 a.m.] anfroholic On the real ones it will be gold colored {Reactions} 🤩 (2) ✨ [2025-12-16 4:15 p.m.] polyfractal looks amazing 🤩 {Reactions} 💜 (2) [2025-12-17 9:57 a.m.] anfroholic I soldered some headers on and put it on a breadboard. It's a little on the large size, but should work great if you need it. {Attachments} 2025-12_media/20251217_000430-DED83.jpg 2025-12_media/20251217_000424-8F87C.jpg 2025-12_media/20251217_000951-D5683.jpg 2025-12_media/20251217_002941-9C101.jpg 2025-12_media/20251217_001045-A33F8.jpg {Reactions} ❤️ (4) [2025-12-17 4:06 p.m.] polyfractal I see the PDK has rules for bumping, is that a thing we could get from GF in the future? https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_09_4.html {Reactions} 💜 [2025-12-17 4:15 p.m.] anfroholic I have also brought up WCSP before. It seems there are a few issues. 1. Just the extra cost, it would require more masks and processes. 2. It seems the people who do the bumping are not interested in the quantities we're doing. 3. Everyone would have to agree on a standard pinout. (I don't see this one as a dealbreaker, but poses some issues when we try to subdivide dies into smaller forms, or probably worse going in the other direction for a larger than standard size like you were asking for for more sram.) It certainly is something that would be very useful if we can devise a way to make it work under all these constraints. [2025-12-17 4:22 p.m.] polyfractal makes sense, thanks @Andrew Wingate! was contemplating chiplet'y things to get more SRAM and simple "bridge" interposers using bumps was a potential candidate 😇 {Reactions} 💜 [2025-12-17 4:26 p.m.] logic_destroyer It's very long [2025-12-17 4:27 p.m.] anfroholic It is, but it's also all 70 pins [2025-12-17 4:27 p.m.] logic_destroyer It's not possible to use a shorter one? [2025-12-17 4:29 p.m.] logic_destroyer I’m using SDRAM in my design {Reactions} 👍 [2025-12-17 4:29 p.m.] anfroholic Of course it is. But you'd have to know the pins you could bridge (VCC, VDD, etc.) This thing was made just to fit whatever anyone did, and more to just make something to play with than something that may actually be useful. [2025-12-17 4:30 p.m.] logic_destroyer Sorry to ask, but why do we need an adapter board? [2025-12-17 4:32 p.m.] anfroholic You don't. This was more of an example for people who get the COB version. Ideally you'd have your own motherboard that did whatever you wanted and just had the mating 70pin mezzanine connector assembled so you could put your chip on however you wanted {Reactions} 😮 [2025-12-17 4:33 p.m.] logic_destroyer COB version is a naked chip? [2025-12-17 4:35 p.m.] anfroholic COB (Chip On Board) The COB is the small 14mm x 16mm pcb that is on the top. Your die would be wirebonded to that and then you can do whatever you want after, but don't have to find a way to wirebond yourself as it's not as accessible as PCBA {Reactions} 😮 (2) [2025-12-17 4:36 p.m.] logic_destroyer How is something like that soldered onto the PCB? [2025-12-17 4:37 p.m.] anfroholic That is wirebonded and covered in clear epoxy [2025-12-17 4:37 p.m.] logic_destroyer Wirebonded from GF? [2025-12-17 4:38 p.m.] anfroholic No they found their own people to do the wirebonding [2025-12-17 4:38 p.m.] logic_destroyer That means we get such PCB with CHIP (COB) [2025-12-17 4:38 p.m.] logic_destroyer ? [2025-12-17 4:40 p.m.] anfroholic You get just this part with your die wirebonded and the mezzanine connector on the back. Everything below that (your own motherboard or breakout board) is on you. {Attachments} 2025-12_media/0005-BCE5B.JPG {Reactions} 👍🏻 [2025-12-17 4:42 p.m.] logic_destroyer I that ok to use only this here? {Attachments} 2025-12_media/image-7731D.png 2025-12_media/image-EBD20.png [2025-12-17 4:42 p.m.] logic_destroyer I need short wires for SDRAM [2025-12-17 4:43 p.m.] logic_destroyer Sorry if I’m asking basic questions. I’m not fully in the loop, and I don’t have much PCB design experience. [2025-12-17 4:47 p.m.] anfroholic For your own die, you can choose whatever pads you want for whatever. These were designed respecting the pad choices chosen by Tiny Tapeout as they had the most ready designs available when we started all this. You're also welcome to design your own COB chip as long as you respect the pad locations on the die, the wirebond pads on the COB PCB, and the location of the mezzanine connector. But going outside the standards will leave all the remaining details to you. [2025-12-17 4:50 p.m.] logic_destroyer Would it be possible to design one universal board for all designs, despite the SDRAM/SRAM differences and other incompatibilities? [2025-12-17 4:51 p.m.] logic_destroyer If it’s not possible, I’ll need to ask you more questions here. My assumption is that I’ll need to integrate your COB board via an adapter PCB, considering the Linux SoC’s requirements. [2025-12-17 4:59 p.m.] anfroholic That's more or less what we have. I am unsure of the exact requirements you're asking for. Maybe there are others here more knowledgable who can answer these questions. [2025-12-17 5:04 p.m.] logic_destroyer All good. I can handle the schematic, and probably the PCB layout too, otherwise I’ll just ask. I also want to provide three PMOD interfaces so I can connect an SD card, Ethernet, and Flash through them. The board only needs the adapter, SDRAM, discrete components, a clock, uart, and the power supplies. {Reactions} 👍 [2025-12-17 5:07 p.m.] logic_destroyer good old times 🙂 {Attachments} 2025-12_media/image-1D69A.png [2025-12-17 5:08 p.m.] logic_destroyer maybe 4 pmods: uart, flash, sdcard, ethernet [2025-12-17 5:13 p.m.] logic_destroyer @Andrew Wingate Last question: do we get the COB with this connector already attached? Which connector we should use for the motherboard? {Attachments} 2025-12_media/image-212F2.png 2025-12_media/image-76A31.png [2025-12-17 5:13 p.m.] anfroholic Yes [2025-12-17 5:14 p.m.] logic_destroyer And which Connector 236 or 262? [2025-12-17 5:15 p.m.] anfroholic Mating connector {Attachments} 2025-12_media/image-C5870.png {Reactions} ❤️ [2025-12-17 5:15 p.m.] logic_destroyer Thank you @Andrew Wingate {Reactions} 👍 [2025-12-17 5:16 p.m.] logic_destroyer I see, that is a pair 🙂 [2025-12-18 2:07 p.m.] anfroholic Came across another packaging tech, an old one. IBM mst https://www.youtube.com/shorts/MZRlHEyirCE {Attachments} 2025-12_media/image-D8A27.png 2025-12_media/image-C0821.png 2025-12_media/image-3C327.png {Embed} EvilmonkeyzDesignz https://www.youtube.com/watch?v=MZRlHEyirCE IBM Eagle, a 1 Mebibit RAM chip 2025-12_media/maxresdefault-84EC6.jpg {Reactions} 👍 (4) [2025-12-18 4:27 p.m.] logic_destroyer @RebelMike @psychogenic @Andrew Wingate Hi pros, I have no idea… any advice for me, please? [2025-12-19 3:24 p.m.] logic_destroyer One more thing I noticed: if an oscillator is used, it has to be an SMD type. According to the dimensions, it still fits underneath the connector. I would have preferred a DIP-4 package so the oscillator could be easily replaced, but it seems I now have to use a 30 MHz SMD oscillator and place it under the connector to keep the trace to the ASIC short. Ideally, the oscillator would have been mounted on top of the connector PCB. [2025-12-19 3:26 p.m.] logic_destroyer I think you have exactly the same problem. How are you planning to solve it? [2025-12-19 3:32 p.m.] rebelmike I think the first iteration of my host board will have an RP2 on it to allow me to test things and play with the frequency. If I make a standalone version I’d probably go for the chip I mentioned before that buffers the output so trace length isn’t important - or see what other people have done and worked 🙂 {Reactions} 👍🏻 [2025-12-19 4:11 p.m.] logic_destroyer Regardless of the solution, the main challenge is the connector and the placement of the oscillator or crystal. Ideally, the oscillator would be mounted on top of the connector board. [2025-12-21 8:32 p.m.] mithro_ @asic destroyer - At some point I think we will have high quality analog IP for clock generation and we can then get rid of things like external oscillators {Reactions} 😮 🙏 [2025-12-21 8:50 p.m.] logic_destroyer @Tim 'mithro' Ansell , this COB adapter doesn’t make sense to me for higher frequencies or SDRAM. I talked to Goran—he sees no issue. The solution is to put both the oscillator and SDRAM on the bottom side. My schematic is done; I’ll do the layout in 2–3 months. [2025-12-21 8:52 p.m.] logic_destroyer I’ll use DIP-8 oscillators, and I want to avoid having any microcontrollers on the board. [2025-12-21 8:54 p.m.] logic_destroyer {Attachments} 2025-12_media/image-32A30.png [2025-12-24 10:07 a.m.] chips4makers AFAIK, you'll always need an external crystal oscillator for accurate clock frequency. I'm not aware of a circuit where oscillation frequency is not dependent on process corner and transistor variations. Alternative is that you need to trim each chip to get wanted clock frequency. [2025-12-24 10:09 a.m.] mithro_ @Chips4Makers aka Staf Verhaegen - Depends on how much accuracy you need. With USB2.0 and a bunch of other protocols you care about the relative drift between two computers and you can get away with using a PLL on the incoming data signals. [2025-12-28 1:06 a.m.] mithro_ @Essen / @Andrew Wingate / @carlfk - https://www.ebay.com/itm/387551726916 {Embed} https://www.ebay.com/itm/387551726916 EVG GEMINI Automated Production Wafer Bonding System | eBay Tooled for 200mm Wafer. 2025-12_media/s-l400-1D60B.jpg {Reactions} 👀 (2) [2025-12-28 3:13 a.m.] anfroholic Awesome! For those interested in what wafer bonding is. Asianometry has a video https://youtu.be/2ACiuKgYUkI {Embed} Asianometry https://www.youtube.com/watch?v=2ACiuKgYUkI Why Wafer Bonding is the Future of Semiconductors Links: - The Asianometry Newsletter: https://www.asianometry.com - Patreon: https://www.patreon.com/Asianometry - Threads: https://www.threads.net/@asianometry - Twitter: https://twitter.com/asianometry 2025-12_media/maxresdefault-973F8.jpg {Reactions} 🎉 (2) [2025-12-28 9:33 p.m.] logic_destroyer {Attachments} 2025-12_media/Screenshot_from_2025-12-28_22-29-01-015DD.png [2025-12-28 9:34 p.m.] logic_destroyer nice [2025-12-29 1:04 p.m.] logic_destroyer Hello, is it true in my case that the chip will consume 13 mW? ``` hd@i9:~/hacking/wafer.space/gf180mcu-kianv-rv32ima-sv32/final $ cat metrics.csv | grep power__tot power__total,0.013211173005402088 ``` [2025-12-29 11:56 p.m.] logic_destroyer @Leo Moser (mole99) @Tim 'mithro' Ansell 😉 [2025-12-30 2:05 a.m.] ravenslofty Most likely not; opensta can use the power information from the liberty file and *guess* what the power usage would be, but for meaningful real-world numbers you would need to give opensta a VCD or something that contains a realistic trace of what you're going to run. Even so, it will probably barely tickle an ammeter, so don't worry too much. [2025-12-30 2:11 a.m.] logic_destroyer As a rough upper bound, can we assume a worst case where all transistors toggle every clock cycle? [2025-12-30 2:30 a.m.] mithro_ @Lofty - That was my assumption too, but @Tholin seem to indicate their GF180MCU chips got pretty warm to the touch. [2025-12-30 2:32 a.m.] tholin At 50MHz, the AS2650v2 gets hot enough to hurt [2025-12-30 2:33 a.m.] tholin I wouldn’t call it "warm" anymore, but firmly in the "hot" territory. [2025-12-30 2:34 a.m.] tholin I hope the COB parts will be able to dissipate heat through the PCB ground plane {Reactions} 😮 [2025-12-30 2:43 a.m.] tholin That’s why I cringe a bit when I see people just have CEN permanently selected on the SRAM macros because I’m pretty sure that that is why I have such incredible heat output. {Reactions} 😮 [2025-12-30 2:47 a.m.] logic_destroyer That could’ve been communicated beforehand, though. [2025-12-30 2:50 a.m.] tholin I still hope that half of that heat output was caravel [2025-12-30 2:51 a.m.] logic_destroyer Why do you think that? [2025-12-30 2:51 a.m.] tholin Because its a whole RISC-V SoC with a bunch of SRAM macros that are also just leaving CEN always active. {Reactions} 😮 [2025-12-30 2:53 a.m.] logic_destroyer How was it at 30 MHz? Do you also have data on the heat output, like how much power your design consumed? [2025-12-30 2:54 a.m.] tholin At 25MHz, its....fine {Reactions} 😀 [2025-12-30 2:55 a.m.] logic_destroyer Do you have data on how much power your board consumed? [2025-12-30 2:57 a.m.] tholin No [2025-12-30 2:58 a.m.] logic_destroyer I have to sleep now. Thanks for the information. [2025-12-30 2:59 a.m.] tholin I have no multimeter that doesn’t max out at 100mA [2025-12-30 12:49 p.m.] chips4makers It's the signals that toggle; if I remember correctly a typical value used for power estimation without a VCD files is using 20% toggle rate on all the signals in a circuit. 100% is really worst case. {Reactions} waferspace 🙏 [2025-12-30 7:54 p.m.] essen__ Started a thread. [2025-12-31 5:38 p.m.] logic_destroyer I don’t know that much about pcb design; for now I’ve got 2-3 months to work on the layout. 😉 {Attachments} 2025-12_media/image-93291.png [2025-12-31 5:40 p.m.] anfroholic Pro tip, Order early, order often. JLCPCB and others have this global standard shipping, and it's like $5 US I would order what you have there, just so you can hold it and look at it. Otherwise looks pretty good so far 👍 {Reactions} ❤️ [2025-12-31 5:50 p.m.] logic_destroyer I was thinking we could do the production with Aisler. Since they support open-source projects, it might be a bit cheaper. I’m in Germany as well, so it’d be convenient. Maybe @Tim 'mithro' Ansell , @Matt Venn , or @psychogenic has a contact there and we can do our PCB order through them. [2025-12-31 6:05 p.m.] logic_destroyer I have six 100 nF caps on the bottom side for decoupling. [2025-12-31 6:06 p.m.] logic_destroyer {Attachments} 2025-12_media/image-E6F48.png [2025-12-31 6:22 p.m.] urish IMHO send the draft version to both Aisler and JLC so you can compare {Reactions} ❤️ [2025-12-31 6:24 p.m.] logic_destroyer I’d also like to have the board assembled. ============================================================== Exported 132 message(s) ==============================================================